In recent years, with miniaturization of semiconductor devices, two kinds of voltages, i.e., an external voltage and an internal voltage, are used and the internal voltage is set lower than the external voltage. Therefore, there is a request for a circuit for converting the logical voltage level of a signal between a circuit driven by the external voltage and a circuit driven by the internal voltage.
Hereinafter, a description will be given of prior arts with respect to a circuit for converting a logical voltage level corresponding to a high power supply voltage to a logical voltage level corresponding to a low power supply voltage (hereinafter referred to as “voltage level conversion circuit”).
Generally, as shown in FIG. 6, the conventional voltage level conversion circuit for converting a logical voltage level corresponding to a high power supply voltage into a logical voltage level corresponding to a low power supply voltage is composed of two stages of NOT circuits.
With reference to FIG. 6, the voltage level conversion circuit 201 comprises a front-stage NOT circuit 201a which is driven by a high power supply voltage VDD1 and inverts an input signal IN, and a rear-stage NOT circuit 201b which is driven by a low power supply voltage VDD2 and inverts an output signal OUT1 of the NOT circuit 201a. 
The front-stage NOT circuit 201a comprises a P channel MOS transistor Qhp11 and an N channel MOS transistor Qhn11 which are connected in series between the high power supply voltage VDD1 and a ground voltage VSS, and a gate of the power supply side transistor Ohp11 and a gate of the ground side transistor Qhn11 are commonly connected. In the NOT circuit 201a, a common connection node of the gates is an input node N1a to which the input signal IN is applied, and a connection point of the power supply side transistor Qhp11 and the ground side transistor Qhn11 is an output node N1b. 
The rear-stage NOT circuit 201b comprises a P channel MOS transistor Qhp12 and an N channel MOS transistor Qhn12 which are connected in series between the low power supply voltage VDD2 and the ground voltage VSS, and a gate of the power supply side transistor Qhp12 and a gate of the ground side transistor Qhn12 are commonly connected. In the NOT circuit 201b, a common connection node of the gates is an input node N2a to which the output signal OUT1 of the front-stage NOT circuit 201a is applied, and a connection node of the power supply side transistor Qhp12 and the ground side transistor Qhn12 is an output node N2b. 
In the above-mentioned voltage level conversion circuit 201, when the input signal IN is supplied, the front-stage NOT circuit 201a inverts the input signal IN and outputs the signal to the rear-stage NOT circuit 201b. Then, the rear-stage NOT circuit 201b further inverts the inverted input signal and outputs the signal.
At this time, since the power supply voltage VDD2 of the rear-stage NOT circuit 201b is lower than the power supply voltage VDD1 of the front-stage NOT circuit 201a, the logical voltage level of the output signal OUT of the rear-stage NOT circuit 201b is lower than the logical voltage level of the output signal OUT1 of the front-stage NOT circuit 201a, whereby the logical voltage level of the input signal is converted from the logical voltage level corresponding to the high voltage power supply to the logical voltage level corresponding to the low power supply voltage.
In the voltage level conversion circuit 201 which converts the logical voltage level of the input signal using the two stages of NOT circuits as described above, generally, the respective NOT circuits 201a and 201b are constituted by VDD1 breakdown voltage transistors having the high power supply voltage as their breakdown voltages, and the rear-stage NOT circuit 201b is driven with the power supply voltage VDD2 which is lower than the power supply voltage VDD1 for driving the front-stage NOT circuit 201a, and the circuit construction thereof is simple.
In the voltage level conversion circuit 201 comprising the two stages of NOT circuits, however, since the threshold values of the VDD1 breakdown voltage transistors constituting the NOT circuits are set at high values, it is difficult to operate the rear-stage NOT circuit 201b with a power supply voltage that is lower than the threshold voltage of the VDD1 breakdown voltage transistor. Although it becomes possible to operate the rear-stage NOT circuit 201b with a power supply voltage that is lower than the threshold voltage of the VDD1 breakdown voltage transistor by using low-threshold-voltage transistors as the transistors constituting the rear-stage NOT circuit 201b. In this case, however, the breakdown voltage of the transistors constituting the rear-stage NOT circuit 201b is lowered, which brings about the possibility of circuit breakage.
Meanwhile, Japanese Published Patent Application No. Hei. 5-14174 (patent literature 1) discloses a level shifter circuit which is able to perform conversion of three values of input and output including high impedance input and output.
FIG. 7 is a diagram for explaining the level shifter circuit disclosed in the patent literature 1.
The level shifter circuit 202 is a circuit for converting the level of an input signal applied to an input terminal 1, and outputting the signal from an output terminal 14.
With reference to FIG. 7, the level shifter circuit 202 comprises a first resistor 2 and a second resistor 3 which are connected in series between a power supply voltage VDD1 and a ground voltage VSS; first and second inverters 4 and 5 having input nodes connected to a connection node n1 of the first and second resistors, respectively; and a level shifter 6 for converting the level of the output of the first inverter 4. The second inverter 5 has a threshold value lower than that of the first inverter 4. Further, the level shifter circuit 202 includes a P channel MOS transistor 12 and an N channel MOS transistor 13 which are connected in series between a power supply voltage VDD2 and the ground voltage VSS, and an output node of the level shifter 6 is connected to a gate of the power supply side transistor 12 while an output node of the inverter 5 is connected to a gate of the ground side transistor 13. An input terminal 1 of the level shifter circuit 202 is connected to a connection node n1 of the first resistor 2 and the second resistor 3, and an output terminal 14 thereof is connected to a connection node n2 of the transistors 12 and 13.
The level shifter 6 includes an inverter 7 to which an output signal of the inverter 4 is applied; a first P channel MOS transistor 8 and a first N channel MOS transistor 10 which are connected in series between the power supply voltage VDD2 and the ground voltage VSS; and a second P channel MOS transistor 9 and a second N channel MOS transistor 11 which are connected in series between the power supply voltage VDD2 and the ground voltage VSS. A connection node n3 of the transistor 8 and the transistor 10 is connected to a gate of the transistor 9, and a connection node n4 of the transistor 9 and the transistor 11 is connected to a gate of the transistor 8. This level shifter 6 converts a VDD1 system signal which is outputted from the inverter 4 and has a logical voltage level corresponding to the high power supply voltage VDD1 into a VDD2 system signal having a logical voltage level corresponding to the low power supply voltage VDD2.
Next, the operation of the level shifter circuit 202 will be described in brief.
In the level shifter circuit 202, when the input voltage applied to the input terminal 1 is low level, the output voltage of the inverter 4 is high level and the output voltage of the inverter 5 is approximately high level. At this time, the output voltage of the inverter 4 is converted from the high level logical voltage of the VDD1 system signal into the high level logical voltage of the VDD2 system signal. Accordingly, the gate voltage VGP of the P channel transistor 12 becomes the low power supply voltage VDD2 while the gate voltage VGN of the N channel transistor 13 becomes the high power supply voltage VDD1, whereby the low level logical voltage (ground voltage) VSS is output from the output terminal 14.
On the other hand, when the voltage applied to the input terminal 1 is high level, the output of the inverter 4 is approximately low level and the output of the inverter 5 is low level. When the output voltage of the inverter 4 is approximately low level, the low level logical voltage remains at the ground voltage even when the output voltage of the inverter 4 is converted by the level shifter 6. Accordingly, the gate voltage VGP of the P channel transistor 12 becomes the ground voltage VSS, and the gate voltage VGN of the N channel transistor 13 becomes the ground voltage VSS, whereby the high level logical voltage VDD2 of the VDD2 system signal is output from the output terminal 14.
Further, when the input voltage applied to the input terminal 1 is an intermediate level between the high level and the low level, the output voltage of the inverter 4 is high level and the output voltage of the inverter 5 is approximately low level. At this time, the output voltage of the inverter 4 is converted by the level shifter 6 from the high level logical voltage of the VDD1 system signal to the high level logical voltage of the VDD2 system signal. Accordingly, the gate voltage VGP of the P channel transistor 12 becomes the low power supply voltage VDD2 and the gate voltage VGN of the N channel transistor 13 becomes the ground voltage VSS. That is, at this time, both of the power supply side transistor 12 and the ground side transistor 13 are in the off states, and the output terminal 14 is in the high-impedance state.
This literature has no specific description about the power supply voltage VDD1 and the power supply voltage VDD2 of the level shifter circuit 202. However, like the voltage level conversion circuit 201 shown in FIG. 6, when the power supply voltage VDD2 is lower than the power supply voltage VDD1, the inverter 5 is driven by the high power supply voltage VDD1, and the high level logical voltage or low level logical voltage of the VDD1 system signal is applied to the gate of the transistor 13, and therefore, the transistor 13 needs a modification such as an increase in the thickness of a gate oxide film so as to have the same breakdown voltage as that of the transistors which constitute the circuit driven by the high power supply voltage VDD1 (VDD1 system circuit). In this case, however, the transistor 13 with the thickness of the gate oxide film being increased is included in the circuit subsequent to the level shifter 6, which is driven by the low power supply voltage VDD2. Therefore, the low power supply voltage VDD2 cannot be set at a value that is lower than the threshold value of the transistor 13, i.e., the threshold value of the transistors of the VDD1 system circuit.
Therefore, in contrast to the voltage level conversion circuit shown in FIG. 6, the level shifter circuit 202 disclosed in literature 1 is a voltage level conversion circuit in which the power supply voltage VDD2 is higher than the power supply voltage VDD1, i.e., which converts the logical voltage level corresponding to the low power supply voltage into the logical voltage level corresponding to the high power supply voltage.
As described above, in the conventional voltage level conversion circuit 201 comprising the two stages of NOT circuits shown in FIG. 6, since the rear-stage NOT circuit having the low power supply voltage VDD2 as a power supply voltage is constituted by the VDD1 breakdown voltage (high breakdown voltage) system transistors, the threshold voltage of the transistors is high, and it is difficult to operate the high breakdown voltage transistors with the low power supply voltage that is lower than the threshold voltage. Therefore, the voltage level conversion circuit 201 impedes reduction in power consumption by low voltage driving and miniaturization of transistors in the semiconductor device.
Further, as described above, the level shifter circuit 202 shown in FIG. 7 is regarded as a circuit for converting a logical voltage level corresponding to a low power supply voltage into a logical voltage level corresponding to a high power supply voltage. When the circuit construction of the level shifter circuit 202 is applied to a voltage level conversion circuit for converting a logical voltage level corresponding to a high power supply voltage into a logical voltage level corresponding to a low power supply voltage, the transistor 13 to which the logical voltage corresponding to the high power supply voltage is applied comes to have a high breakdown voltage with a thick gate oxide film, and thereby the low power supply voltage cannot be lower than the threshold value of the transistor having the high power supply voltage as a breakdown voltage.